Prior art FIG. 1 illustrates a graphics pipeline 100, in accordance with the prior art. As shown, the graphics pipeline 100 is shown logically to include a plurality of modules 102 for performing various graphics processing operations. Just by way of example, such modules 102 may include a front end module 103 for receiving graphics data 109 in the form of primitives, and determining the manner and order in which pixels defining each primitive will be processed in order to render an image of such primitives.
Still yet, the modules 102 may include various other graphics processing modules including, but not limited to vertex and pixel shaders 105 for determining the surface properties of a vertex and pixel (or fragment, etc.), respectively. Of course, additional graphics processing modules may be included for providing various other graphics processing capabilities.
In use, such graphics processing modules 102 process the graphics data 109 for storage in a frame buffer 104 which, in turn, feeds a display 106. As graphics processing capabilities have advanced, the contents of the frame buffer 104 has often been “fed back” into various previous modules 102 of the graphics pipeline 100 for being re-processed in different ways. Such feed back 108 is shown in FIG. 1. Just by way of example, “render-to-vertex” and “render-to-texture” processing may be performed on the rendered graphics data 109 in the frame buffer 104 for enhancing an ultimately displayed output.
It should be noted that, during the course of such advanced processing, an inherent difficulty arises when first graphics data being operated upon by subsequent modules 102 in the graphics pipeline 100 produces first results in the frame buffer 104 that are required by previous modules 102 operating on second graphics data. In such situations, such results from the first graphics data may not be readily available when needed by processing of the second graphics data, thereby creating complications. For example, unavailability of necessary graphics data, conflicting requests for the same graphics data, etc. may be problematic to effective graphics processing.
To date, these and other related problems have been addressed by the aforementioned front end module 103. In particular, after first graphics data is input into the graphics pipeline 100, the front end module 103 typically waits until such first graphics data has been completely processed by all of the relevant graphics processing modules 102 in order to flush the results from the graphics pipeline 100, before admitting second graphics data. By this feature, it is ensured that the aforementioned results of the first graphics data is available if required for graphics processing in conjunction with the second graphics data by previous modules 102, etc.
Unfortunately, such waiting creates an inherent delay that impacts the ability of the graphics pipeline 100 to operate in a fast-paced manner. There is thus a need for overcoming these and/or other problems associated with the prior art.